Original Assignee NEC Corp Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.) ( en Inventor Katsuji Kimura Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.) Granted Application number US10/137,298 Other versions US6657485B2 Google Patents Linear voltage subtractor/adder circuit and MOS differential amplifier circuit thereforĭownload PDF Info Publication number US20020158686A1 US20020158686A1 US10/137,298 US13729802A US2002158686A1 US 20020158686 A1 US20020158686 A1 US 20020158686A1 US 13729802 A US13729802 A US 13729802A US 2002158686 A1 US2002158686 A1 US 2002158686A1 Authority US United States Prior art keywords voltage mos mos transistors transistors differential Prior art date Legal status (The legal status is an assumption and is not a legal conclusion. Google Patents US20020158686A1 - Linear voltage subtractor/adder circuit and MOS differential amplifier circuit therefor US20020158686A1 - Linear voltage subtractor/adder circuit and MOS differential amplifier circuit therefor
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